EDGE2=EDGE2_0, IEN3=IEN3_0, DEN3=DEN3_0, DEN2=DEN2_0, EDGE3=EDGE3_0, IEN2=IEN2_0, STS2=STS2_0, STS3=STS3_0
Crossbar A Control Register 1
| DEN2 | DMA Enable for XBAR_OUT2 0 (DEN2_0): DMA disabled 1 (DEN2_1): DMA enabled |
| IEN2 | Interrupt Enable for XBAR_OUT2 0 (IEN2_0): Interrupt disabled 1 (IEN2_1): Interrupt enabled |
| EDGE2 | Active edge for edge detection on XBAR_OUT2 0 (EDGE2_0): STS2 never asserts 1 (EDGE2_1): STS2 asserts on rising edges of XBAR_OUT2 2 (EDGE2_2): STS2 asserts on falling edges of XBAR_OUT2 3 (EDGE2_3): STS2 asserts on rising and falling edges of XBAR_OUT2 |
| STS2 | Edge detection status for XBAR_OUT2 0 (STS2_0): Active edge not yet detected on XBAR_OUT2 1 (STS2_1): Active edge detected on XBAR_OUT2 |
| DEN3 | DMA Enable for XBAR_OUT3 0 (DEN3_0): DMA disabled 1 (DEN3_1): DMA enabled |
| IEN3 | Interrupt Enable for XBAR_OUT3 0 (IEN3_0): Interrupt disabled 1 (IEN3_1): Interrupt enabled |
| EDGE3 | Active edge for edge detection on XBAR_OUT3 0 (EDGE3_0): STS3 never asserts 1 (EDGE3_1): STS3 asserts on rising edges of XBAR_OUT3 2 (EDGE3_2): STS3 asserts on falling edges of XBAR_OUT3 3 (EDGE3_3): STS3 asserts on rising and falling edges of XBAR_OUT3 |
| STS3 | Edge detection status for XBAR_OUT3 0 (STS3_0): Active edge not yet detected on XBAR_OUT3 1 (STS3_1): Active edge detected on XBAR_OUT3 |